With continuous development of semiconductor process technology, the process node gradually decreases, and the gate-last process has been widely applied in order to obtain the ideal threshold voltage and to improve device performance. However, when critical dimension (CD) of semiconductor devices further decreases, even with the gate-last process, conventional MOS field-effect-transistor (MOSFET) structure can no longer meet the requirements on the device performance, such as threshold voltage (VT) variability. As an alternative to conventional devices, multi-gate devices have been gaining widespread attentions.
A fin field-effect-transistor (Fin FET) is a common multi-gate device. FIG. 1 shows a three-dimensional structural diagram of an existing Fin FET. As shown in FIG. 1, the Fin FET includes: a semiconductor substrate 10; a protruding fin 14 formed on the semiconductor substrate 10 generally through etching; a dielectric layer 11 covering the semiconductor substrate 10 and parts of sidewalls of fin 14; and a gate structure 12 across the fin 14 and covering the top and sidewalk of the fin 14. The gate structure 12 includes a gate dielectric layer (not shown) and a gate electrode formed on the gate dielectric layer (not shown). The regions of the top and sidewalls of the fin 14 covered by the gate structure 12 become the channel regions, i.e., with multiple gates. Thus, the drive current can be increased and the device performance can be improved.
However, when the process node is further reduced, such existing fin FET structure may still have device performance issues. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.